EECE 412 : Adv Digital Systems Design Lab

Laboratory projects will use a PC based Computer Aided Design Tool environment that supports hardware description languages (HDL) such as VHDL and Verilog for design, simulation, and synthesis of logic systems. Early lab exercises (mini projects) will use SSI/MSI chips, then HDL-based design tools and associated methodologies will be introduced to design, simulate, and synthesize complex digital systems for implementation with Programmable Logic Devices and Field Programmable Gate Arrays (FPGA). Teams of two or three students will specify and undertake design projects.